The present invention relates generally to internal wiring of a semiconductor apparatus and more particularly to a semiconductor apparatus fabricated using a multilayer wiring configuration.
Recent efforts have been made in the semiconductor industry to develop improved micro-circuitry in order to enhance capabilities of semiconductor apparatuses. In highly integrated semiconductor apparatuses, the percentage of chip area used for wiring circuitry or interconnect has been increasing. Such wiring trends have been noticeable in various types of devices such as semiconductor memory devices and gate arrays.
As the technology for fabricating micro-circuit device elements in a semiconductor apparatus advances, the operating speed of the gating circuitry increases due to the decreased on-resistance of transistors such as metal-oxide semiconductor field effect transistors (MOSFETs). However, the width of the wiring lines used as an interconnect for the switching circuitry also becomes finer. The finer wiring requires smaller minimum dimensions such as width and/or thickness in the wiring layer. Due to the finer wiring, the resistance per unit length of the wiring circuit can increase. Also, due to the finer micro-circuit device elements, there can be an increased number of gating circuits on a chip and thus, it can be difficult to shorten the lengths of wiring circuitry due to the complexity of the layout. These factors can cause an increase in the RC (resistance-capacitance) time constant and adversely affect the overall operating speeds of the semiconductor apparatus.
In such densely integrated semiconductor apparatuses, decreasing the chip area by reducing wiring spacing is limited. Therefore, multi-layer wiring schemes have been used in which wiring layers are vertically separated by intervening insulation layers. The effectiveness of micro-fabrication of device elements can be improved by incorporating a multi-layer wiring process to provide multiple wiring layers.
In the process of manufacturing a semiconductor apparatus incorporating a multi-layer wiring scheme, a wiring layer having a high sheet resistance (xcexa9/xe2x96xa1) may sometimes be used. For example, a first wiring layer can be a wiring layer that makes contact to and provides wiring for device diffusion layers. A high melting point metal (TiN/Ti, TiN, TiW, W, or the like) that has a high sheet resistance can be used as a material for the first wiring layer. In this example, Ti represents titanium, TiN represents titanium nitride, TiW represents titanium tungsten, and W represents tungsten.
One of the reasons for using a high melting point metal in the first wiring layer is related to the process of making memory cells, as just one example. In the case of a semiconductor memory such as a dynamic random access memory (DRAM) incorporating a capacitor over bit line (COB) memory cell, after fabricating the first wiring layer (which can be used for the bit lines), a high temperature treatment can be carried out to form a capacitor for storing charge in each memory cell. Thus, a high melting point metal is used as a material for the first wiring layer, due to its ability to withstand such a heat history. There are methods for forming the first wiring layer after making the capacitor of the memory cells, however, these methods can present a problem by increasing the capacitance of bit lines and/or reducing cell capacitance. Thus, the aforementioned method is used more frequently.
Referring now to FIG. 7, a conventional memory array is set forth in a block schematic diagram and given the general reference character 700. Conventional memory array includes capacitor over bit line (COB) memory cells MC connected by a bit line BL.
For example, if the first wiring layer of a three wiring layer configuration is used as an interconnect for a peripheral circuit of a semiconductor apparatus whose memory cell array has been fabricated by the above process, the resulting device can suffer from inferior properties including a slower operational speed due to the high resistance of the interconnect wiring.
For the reasons stated above, multi-layered wiring structures have been implemented in which, within functional blocks having device elements, a second wiring layer is used for an interconnect in a vertical direction and a third wiring layer is used for an interconnect in a horizontal direction. Such a configuration will now be discussed with reference to FIG. 5.
Referring now to FIG. 5, a top view of a schematic diagram of a conventional functional circuit block in a conventional semiconductor apparatus is set forth and given the general reference character 500. The conventional functional circuit 500 includes a plurality of MOSFETs having gate electrodes 501 and diffusion layers 502 for forming source and drain regions. Conventional functional circuit block 500 also includes, first wiring layer M1 (not shown), second wiring layer M2 and third wiring layer M3.
The material for the first wiring layer M1 is a high melting point metal and the material for the second and third layers is aluminum. Aluminum exhibits approximately a difference of two orders of magnitude lower sheet resistance than the high melting point metal.
However, in a semiconductor apparatus having conventional functional circuit blocks 500 arranged in a lattice or matrix configuration, it is not possible to use the second wiring layer M2 in the horizontal direction. Therefore, it is necessary to use the third wiring layer M3 for connecting to other function circuit blocks in the horizontal direction. In this case, the third wiring layer M3 is also used for internal wiring in a central region 510, and therefore, it is not possible to form wiring for mutual connections of blocks in the central region 510. For these reasons, a wiring region or wire routing channel disposed in the vertical direction between rows of blocks and having intra-block signal wiring running horizontally must be created to allow connections between functional circuit blocks using the third wiring layer M3.
Thus, an extra wiring region is required for the conventional semiconductor apparatus according to FIG. 5. This extra wiring region can increase the chip size by requiring routing regions over areas in which no device elements such as MOSFETs exist. This increase in chip size reduces the number of chips manufactured per wafer, thus increases production costs.
To prevent an increase in chip size, the first wiring layer M1 can be used for wiring in the vertical direction for short distances and the second wiring layer M2 can be used for connecting elements when longer wiring lengths are needed. Such a configuration will now be discussed with reference to FIG. 6.
Referring now to FIG. 6, a top view of a schematic diagram of a conventional functional circuit block in a conventional semiconductor apparatus is set forth and given the general reference character 600. The conventional semiconductor apparatus includes a plurality of MOSFETs having gate electrodes 601 and diffusion layers 602 for forming source and drain regions. Conventional functional circuit block 600 also includes, first wiring layer M1, second wiring layer M2 and third wiring layer M3.
It is noted that in FIG. 6, first wiring layer M1 is used for interconnect in the vertical direction within a conventional functional circuit block 600. The second wiring layer M2 is used for interconnect within the horizontal direction within the conventional function circuit block 600. This allows a central region 610 to be used for block to block interconnections without the addition of a separate routing channel outside the parameters of the conventional function circuit block 600.
However, when high resistive wiring, such as first wiring layer M1, is used for interconnections between device elements even for a short wiring distance can adversely affect the performance (operating speed and other parameters) of the functional block. This is particularly true as device element geometries are reduced allowing circuitry to operate at higher frequencies.
In view of the above discussion, it would be desirable to provide a semiconductor apparatus and a manufacturing method for the semiconductor apparatus to form wiring within each functional circuit block without affecting the performance of the apparatus.
According to the present embodiments, a semiconductor apparatus incorporating a multi-layer wiring structure can include a functional circuit block having device elements that can be electrically connected with a wiring layer formed within a wiring region for wirings disposed in a first direction and a wiring region for wirings disposed in a second direction.
According to one aspect of the embodiments, the first direction can be orthogonal to the second direction.
According to another aspect of the embodiments, each device element can include a diffusion region. A wiring layer can produce electrodes electrically connected to diffusion regions of device elements.
According to another aspect of the embodiments, a first wiring layer providing electrodes to diffusion regions can be disposed in a first direction in parallel with and electrically connected to a second wiring layer disposed in a first direction in a wiring region.
According to another aspect of the embodiments, the wiring layer providing electrodes to diffusion regions can have a higher resistance than the wiring layer disposed in a first direction in a wiring region and in a second direction in another wiring region.
According to another aspect of the embodiments, the wiring layer providing electrodes to diffusion regions can have a higher melting point than the wiring layer disposed in a first direction in a wiring region and in a second direction in another wiring region.
According to another aspect of the embodiments, the circuit blocks can be arranged in a first direction and/or a second direction on the surface of a semiconductor substrate.
According to another aspect of the embodiments, the wiring layer providing electrodes to diffusion regions can be used to provide bit lines in a memory array.
According to another aspect of the embodiments, the memory array can include DRAM cells having a capacitor over bit line structure.
According to another aspect of the embodiments a method may include forming a semiconductor apparatus by electrically connecting functional blocks with a multi-layer wiring configuration in which each functional block includes a first wiring region having a wiring layer disposed in a first direction and a second wiring region having the wiring layer disposed in a second direction.
According to another aspect of the embodiments, the method for forming a semiconductor apparatus includes forming a diffusion layer associated with device elements on the surface of a substrate.
According to another aspect of the embodiments, the method for forming a semiconductor apparatus includes forming a first interlayer film providing an insulator between a first wiring layer and the substrate.
According to another aspect of the embodiments, the method for forming a semiconductor apparatus includes forming a first wiring layer to produce electrodes electrically connected to diffusion layers of device elements.
According to another aspect of the embodiments, the method for forming a semiconductor apparatus includes forming a second insulation film providing an insulator between the first wiring layer and a second wiring layer.
According to another aspect of the embodiments, the method for forming a semiconductor apparatus includes forming a second wiring layer wherein for each functional block a first wiring region provides electrical connections using the second wiring layer in a first direction only and a second wiring region provides electrical connections using the second wiring layer in a second direction only.
According to another aspect of the embodiments, the method for forming a semiconductor apparatus includes the first wiring layer having a higher sheet resistance and melting point than the second wiring layer.
According to another aspect of the embodiments, the method for forming a semiconductor apparatus includes forming bit lines for a memory array when forming the first wiring layer.